The present invention relates to a semiconductor integrated circuit device and a defect relieving method therefor and, more particularly, to technologies which are effective when used in a dynamic RAM (i.e., Random Access Memory) having a large storage capacity such as 64 Mbits, although the invention is not limited to this, and a defect relieving method therefor.
There has recently been developed a dynamic RAM (which may be referred to as "DRAM") which has a large storage capacity of about 16 Mbits. This dynamic RAM is exemplified on pages 67 to 81 of "Nikkei Micro Device" published on Mar. 1, 1988 by NIKKEI McGRAW-HILL.
A semiconductor memory device such as the DRAM using MISFETs includes a memory cell array having a plurality of memory cells arranged in a matrix form. In case data is to be written in or read out from an arbitrary memory cell of the DRAM, a row address decoder and a column address decoder select the row and column corresponding to address signals coming from the outside to address that memory cell. In response to the selection signals from the row address decoder, the word driver drives the word line of the row to be selected to a selection level. The aforementioned word line acts as the gate electrode of the selected MISFET of the memory cell. The aforementioned gate electrode acts as a mask for forming the source or drain electrode of the selected MISFET by an ion implantation. The aforementioned gate electrode is made of polycrystalline silicon, for example, because it has to stand the heat of the heat treatment after the ion implantation.
To attain a higher degree of integration of the aforementioned semiconductor memory device, the memory cell array becomes larger so that the word lines become longer. Since the polycrystalline silicon has a high resistance, the word lines take an extremely high resistance so that the CR time constant is enlarged. This causes a delay in the signal transmission time from the word driver. Thus, it is possible to adopt the technology, by which word shunting lines made of a material having a low resistance such as aluminum are disposed close to and in parallel with the aforementioned word lines made of polycrystalline silicon so that the transmission delay of word line drive signals may be reduced by connecting the aforementioned word shunting lines and the aforementioned word lines.
Incidentally, the word shunting lines are described in Japanese Patent Laid-Open No. 106693/1977.
In accordance with the aforementioned large storage capacity, the memory chips are naturally large-sized. Accordingly, in a dynamic RAM having its storage capacity enlarged to about 64 Mbits, the signal transmission speed is dropped as the wiring length is increased by making the elements (e.g. the wiring layer and the circuit elements) finer and by having the wiring lines lugged around the chip. As a result, the DRAM intended to achieve the aforementioned high storage capacity has to take into special consideration the drop in the operation speed due to the aforementioned signal delay. In other words, a new technology different from the techniques used in the prior art for about 1 Mbit or 4 Mbits is required for realizing the large storage capacity of about 64 Mbits.
In order to improve the degree of integration of the semiconductor memory device, on the other hand, it is necessary to reduce the size of the memory cell and the width of the wiring lines such as the word shunting lines. In the DRAM of 16 Mbits, for example, it is expected that the word shunting lines have a width of about 0.6 to 0.8 .mu.m. The word shunting lines are frequently made of aluminum. In case the electric wiring lines are made of thin aluminum, they can easily be broken by the so-called "electro-migration phenomena" (which will be shortly referred to as "EMD"), in which wiring metal will migrate while exchanging kinetic energy with the carriers. We have also found another problem that the wiring materials are broken by the so-called "stress migration" (which will be shortly referred to as "SMD"), in which a strain is caused in the wiring materials by the stress coming from the inter-layer insulating films.